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Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

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5 Author(s)
P. R. Morrow ; Components Res., Intel Corp., Hillsboro, OR, USA ; C. -M. Park ; S. Ramanathan ; M. J. Kobrinsky
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The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 μm×5 μm and 6 μm×40 μm. The top wafers were thinned to different thicknesses in the range 5 to 28 μm. Through-silicon-vias (TSVs) and backside metallization were used to enable electrical testing of both wafers in the Cu-stacked configuration. We tested individual transistors in the thinned silicon of bonded wafer pairs where the thinned silicon thickness ranged from 14 to 19 μm. All results showed that both n- and p-channel transistors preserved their electrical characteristics after Cu bonding, thinning, and TSV integration. We also demonstrated the functionality of stacked 65-nm 4-MB SRAMs by independently testing the cells in both the thinned wafer and the bottom wafer. For the SRAM, we tested a wider thinned wafer thickness range from 5 to 28 μm. On all tested samples, we did not find any impact to the electrical performance of the arrays resulting from the three-dimensional (3-D) integration process. The stacked SRAM is an experimental demonstration of the use of 3-D integration to effectively double transistor packing density for the same planar footprint. The results presented in this letter enable further exploratory work in high-performance 3-D logic, which takes advantage of the improved interconnect delays offered by this Cu-bonding stacking scheme integrated with modern CMOS processes.

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IEEE Electron Device Letters  (Volume:27 ,  Issue: 5 )