Skip to Main Content
This letter reports InP/In0.53Ga0.47As/InP double heterojunction bipolar transistors (DHBTs) employing an N+ subcollector and N+ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance Ccb associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N+ subcollector that lies underneath the base ohmic contact, as well as compensate the ∼1-7×10-7 C/cm2 surface charge at the interface between the indium phosphide (InP) substrate and the N$collector drift layer. By implanting the subcollector, Ccb associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces Ccb by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz fτ and 403-GHz fmax. The dc current gain β≈38, BVceo=6.0 V, BVcbo=5.4 V, and Icbo<50 pA at Vcb=0.3 V.