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Branch trace compression for snapshot-based simulation

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2 Author(s)
Barr, K.C. ; MIT Comput. Sci. & Artificial Intelligence Lab., Cambridge, MA, USA ; Asanovic, K.

We present a scheme to compress branch trace information for use in snapshot-based microarchitecture simulation. The compressed trace can be used to warm any arbitrary branch predictor's state before detailed microarchitecture simulation of the snapshot. We show that compressed branch traces require less space than snapshots of concrete predictor state. Our branch-predictor based compression (BPC) technique uses a software branch predictor to provide an accurate model of the input branch trace, requiring only mispredictions to be stored in the compressed trace file. The decompressor constructs a matching software branch predictor to help reconstruct the original branch trace from the record of mispredictions. Evaluations using traces from the Journal of ILP branch predictor competition show we achieve compression rates of 0.013-0.72 bits/branch (depending on workload), which is up to 210× better than gzip; up to 52× better than the best general-purpose compression techniques; and up to 4.4× better than recently-published, more general trace compression techniques. Moreover, BPC-compressed traces can be decompressed in less time than corresponding traces compressed with other methods.

Published in:

Performance Analysis of Systems and Software, 2006 IEEE International Symposium on

Date of Conference:

19-21 March 2006