Hierarchical management of VLSI cells at different description levels

The implementation of a data structure that permits a VLSI designer to operate at different description levels during the design of a chip is addressed. This data structure has been realized using software tools like object-oriented programming, which allow the creation of very modular programs. For the input/output program operations, the EDIF format has been used. To manage the data structure, suitable graphics, which permit the user to access data structure through the use of windows and menus, have been developed.<
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