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A new test generation approach is proposed for circuits having a a size parameter (e.g., operand size), that can be varied to obtain designs of different sizes. Under this approach, test generation is only performed for small versions of the target circuit, where test generation is fast and high-quality test sets can be obtained. The test sets for these small circuits are then studied, and analytical rules are derived to capture their common features. Finally, the rules derived are applied to obtain a high-quality test set for the large target circuit. The method, its feasibility and limitations are described in this work.