Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Technology Mapping for Low Power

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Tiwari, V. ; Dept. of EE, Princeton Univ ; Ashar, P. ; Malik, S.

The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.

Published in:

Design Automation, 1993. 30th Conference on

Date of Conference:

14-18 June 1993