A thermal, mechanical, and electrical study of voiding in the solder die-attach of power MOSFETs

Large area die-attach defects have been shown to increase the thermal impedance of power semiconductor devices. The changes in thermal performance are simulated and measured in the silicon die using one-, two-, and three-dimensional methods. Experimental measurements for devices with various levels of die-attach void growth are presented. This data is then correlated with finite element thermal modeling to improve the estimate of peak die temperature for voided semiconductor devices. The results present a complete understanding of the heat flow within the voided semiconductor package with an estimate of its impact on performance over its lifetime.