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A transistor-level test strategy for C/sup 2/MOS MOUSETRAP asynchronous pipelines

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2 Author(s)
Feng Shi ; Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA ; Y. Makris

We discuss a transistor-level test methodology for C2MOS asynchronous pipelines. Unlike their static CMOS counterparts, wherein testing for stuck-at faults and compliance to a few timing constraints typically suffices, dynamic asynchronous pipelines present new challenges which require more elaborate test solutions. More specifically, many gate-level input/output stuck-at faults of a static pipeline style translate into transistor-level stuck-open/stuck-short faults in the dynamic C2MOS version. Therefore, test methods for transistor-level faults are required for dynamic asynchronous pipelines. To this end, we propose a methodology for testing both gate-level stuck-at faults and transistor-level stuck-open/stuck-short faults in C2MOS pipelines. The proposed method does not employ additional hardware and is capable of detecting both gate-level and transistor-level faults, as we demonstrate on the C2MOS version of MOUSETRAP

Published in:

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)

Date of Conference:

13-15 March 2006