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Functional verification is a critical and time-consuming task in every ASIC design schedule. To make functional verification more efficient, many design teams have adopted assertion-based verification (ABV) with formal verification technologies. We have educated and helped many design teams to deploy ABV. In the process, we have uncovered hard-to-verify structures for which traditional simulation- based verification is inefficient - and for which formal verification is a better approach. We recommend design teams to address such verification hot spots with formal verification. In this paper, we describe several of them, the properties involved, and the methodologies we deployed.