Application Specific Instruction Set Processor Microarchitecture for UTMS-FDD Cell Search

This paper introduces the microarchitecture of an application specific instruction set processor (ASIP) targeted for cell search functions in an UMTS-FDD mobile terminal. The suggested architecture is used for synchronization of the mobile terminal to the base transceiver stations and for calculating impulse response measurements to form channel estimates. The ASIP was modeled using LISA 2.0 architecture description language. The critical parts of the cell search functions were identified and the processor hardware and instruction set optimized accordingly. The ASIP is programmable in C. The functionality of the architecture was verified using a cycle-accurate instruction set simulator and VHDL simulator. Synthesizable VHDL code was automatically generated from the LISA description. The ASIP was evaluated based on the cycle count, operating frequency, area and power consumption. The performance was compared to real-time requirements. It is shown that the proposed architecture poses a programmable solution for implementing the computationally demanding algorithm.