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Proof of Concept for Low-power Digital Asynchronous IC Design

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3 Author(s)
T. J. Zetterman ; Computing Architectures Laboratory Nokia Research Center Helsinki, Finland, Email: ; J. T. Liimatainen ; J. T. Alamaunu

Asynchronous IC technology research has been carried out in Nokia Research Center in the project, where four different test chips were manufactured and measured. The measurement results indicate significant power savings compared to synchronous circuits. This paper presents our asynchronous design flow, test design, and the measurement result of manufactured test chip samples.

Published in:

2005 International Symposium on System-on-Chip

Date of Conference:

17-17 Nov. 2005