VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks

The inherent parallelism of artificial neural networks (ANNs) introduces several difficulties for its software implementation because of the sequential nature of von Neumann architectures. In contrast, hardware implementations offer the possibility to explore the massive parallelism implicit in this model. Also, due to the dynamic nature of ANN's synapses, a flexible hardware platform is required for obtaining efficient solutions. Implementations of ANNs in FPGAs overcome the lack of flexibility of ASICs, and are the most adequate technology for this task. One important question in this field is how to quickly and efficiently evaluate several alternative implementations taking into account the area and timing restrictions of the circuit. This paper presents a flexible high level description and synthesis tool called VANNGen, which allows the designer to explore different hardware implementations of ANNs. In addition, the user can generate synthesizable VHDL code for the Xilinx and Altera FPGA devices