Skip to Main Content
With the exponential explosion in chip complexity there is a growing need for high level design aids. A preliminary experiment was conducted in mating a hierarchical, top-down DA system for data paths with an existing IC placement and router. Nine designs ranging in complexity from 7 to 150 register transfers were synthesized. Strong correlations were observed between high level, abstract measures and final placed and routed chip area. It was observed that use of logic primitives of a moderate level abstraction yielded a 50% savings in placed and routed chip area.