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A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers

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9 Author(s)
Arias, J. ; Dpto. de E. y Electron., Univ. de Valladolid, Spain ; Kiss, P. ; Prodanov, V. ; Boccuzzi, V.
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We present an experimental continuous-time complex delta-sigma multi-bit modulator, implemented in standard 0.25-μm CMOS technology and meeting all major requirements for application in IEEE 802.11a/b/g wireless LAN receivers. The clock frequency is 320 MHz, producing an oversampling ratio of 16 for 20 MHz channel bandwidths. The modulator supports two operation modes for zero-IF and low-IF receiver architectures respectively, requires a single 2.5-V power supply, and dissipates only 32 mW of power. The measured peak signal-to-noise ratio is 55 dB. Further experimental results using sine-wave and OFDM test signals are also presented.

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Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 2 )