By Topic

A comprehensive SoC design methodology for nanometer design challenges

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
R. R. Kumar ; Magma Design Autom., Bangalore, India ; R. Bedi ; R. Rajagopal ; N. Guruprasad
more authors

Summary form only for tutorial. SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. This tutorial highlights nanometer chip design challenges and recommends a tool independent design flow which meets the current trends. Covered are ASIC synthesis concepts along with integrated design for testability flow. The focus here is on different approaches to address the convergence challenges during synthesis along with some of the key design optimizations and transformations which would directly impact quality of results (QoR) post P&R. Verification methodology is also discussed. New verification languages and structural tools for linting and code coverage, latest trends in functional verification from the methodology and technology perspective are covered. Also new verification methodology that identifies and provides definition of metrics for functional coverage is reviewed.

Published in:

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)

Date of Conference:

3-7 Jan. 2006