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SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. This tutorial highlights nanometer chip design challenges and recommends a tool independent design flow which meets the current trends. Covered are ASIC synthesis concepts along with integrated design for testability flow. The focus here is on different approaches to address the convergence challenges during synthesis along with some of the key design optimizations and transformations which would directly impact quality of results (QoR) post P&R. Verification methodology is also discussed. New verification languages and structural tools for linting and code coverage, latest trends in functional verification from the methodology and technology perspective are covered. Also new verification methodology that identifies and provides definition of metrics for functional coverage is reviewed.
Date of Conference: 3-7 Jan. 2006