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The advent of nanometer design process has enabled the integration of multi-million gates with a variety of functionality as a system-on-chip (SoC). The demand for high levels of integration in SoCs are fueled by a strong demand in consumer oriented products for hand held computing, multimedia and other communication products. For these products, power budget is a very critical factor deciding the battery life, size and weight of the portable devices. Designers need to use energy reduction techniques to support as many design features and functions and still keep within the system power budget. The tutorial presents a comprehensive introduction to low power design techniques, and challenges in various facets of the design process. We present an in-depth introduction to concepts with a holistic view to overcome the various challenges and present strategies with a practical approach to the key issues in the design of low power solutions. All the techniques are discussed with practical examples.
Date of Conference: 3-7 Jan. 2006