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Enhanced write performance of a 64-mb phase-change random access memory

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13 Author(s)
Hyung-Rok Oh ; SRAM Team, Samsung Electron. Co. Ltd., Gyeonggi-Do, South Korea ; Beak-Hyung Cho ; Woo Yeong Cho ; Sangbeom Kang
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The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-μm CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 1 )

Date of Publication:

Jan. 2006

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