Referenced Items are not available for this document.
To help overcome limits to the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low-Vth nMOS transistors used to achieve both low-VDD and high-speed operations. For the same speed, the area of our proposed SRAM is 23% smaller than that of a conventional SRAM. Further, we have fabricated a 64-kb SRAM macro using 90-nm CMOS technology and have obtained with it a minimum VDD of 440 mV and a 20-ns access time with a 0.5-V supply.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
1
)
Date of Publication: Jan. 2006
- Page(s):
- 113 - 121
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8710506
- Digital Object Identifier :
- 10.1109/JSSC.2005.859030
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 27 December 2005
- Issue Date :
- Jan. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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