Referenced Items are not available for this document.
Concordant memory design incorporates fluctuation in device parameters statistically into signal-to-noise ratio analysis in DRAM. In this design, the effective signal voltage of all cells in a chip is calculated, and the failed bit count of the chip is estimated. The proposed design approach gives us a quantitative evaluation of the memory array and assures 1.4-V array operation of 100-nm-1-Gb DRAM. Calculated dependence of the failed bit count on the array voltage is in close agreement with measured data for the 512-Mb DRAM chip.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
1
)
Date of Publication: Jan. 2006
- Page(s):
- 107 - 112
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8710505
- Digital Object Identifier :
- 10.1109/JSSC.2005.859023
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 27 December 2005
- Issue Date :
- Jan. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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