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Intellectual property (IP) reuse is essential for meeting the challenges of system-on-a-chip (SoC) design productivity improvement, design quality and meeting time-to-market goals. Recent trend in the design of complex SoC is doing a joint development with the customer, where it is required to integrate some of their IPs. In such a scenario, the usual paradigm followed for reuse has to be enhanced beyond the state of the art to meet the design goals. This paper describes the reuse framework that has been successfully applied during such a joint development program. The methodology consists of imposing a specified degree of compliance for internal checklists comprising of code quality, design quality, verification quality, and testability checks, and aligning on the goals for design verification and test coverage. Customized enhancements to the IPs to meet the SoC design goals are presented.