By Topic

A low-power FIR filter using combined residue and radix-2 signed-digit representation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
A. Lindahl ; Dept. of Comput. Sci. & Eng., Chalmers Univ. of Technol., Goteborg, Sweden ; L. Bengtsson

This paper presents a FIR filter combining residue (RNS) and radix-2 signed digit (SD) representation. RNS offers parallelization of the computations and SD carry-free additions. The moduli set {2n-1, 2n, 2n+1} is used reducing the complexity of the RNS arithmetic units. The evaluated filters have 8, 12 and 16 taps, binary word lengths between 16 and 64 bits, and have been synthesized using a UMC 0.13 μm CMOS cell library with 8 metal layers. Power, delay, and area comparisons are made with equivalent 2's complement designs. The area-delay and area-delay-power products shows that reduction in both power and area at the same filter throughput can be expected.

Published in:

8th Euromicro Conference on Digital System Design (DSD'05)

Date of Conference:

30 Aug.-3 Sept. 2005