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BIST technique for GALS systems

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2 Author(s)
M. Krstic ; IHP, Frankfurt, Germany ; E. Grass

In this paper a test technique based on the built-in self-test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for globally asynchronous locally synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP's 0.25 μm CMOS technology and test results are presented.

Published in:

8th Euromicro Conference on Digital System Design (DSD'05)

Date of Conference:

30 Aug.-3 Sept. 2005