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Broad-band phase-locked loops (PLLs) are proposed for burst-mode clock and data recovery in optical multiaccess networks. Design parameters for a charge-pump PLL-based clock and data recovery (CDR) with fast phase acquisition are derived using a time-domain model that does not assume narrow loop bandwidth or small phase errors. Implementation in a half-rate CDR circuit confirms a clock phase acquisition time of 40 ns, or 100 bits at 2.488-Gb/s rate, and data recovery at 1.244-Gb/s rate with a bit-error rate of 1×10-10 (214-1 pseudorandom binary sequence with Manchester-encoding). The CDR was fabricated in complementary metal-oxide-semiconductor 0.18-μm technology in an area of 1×1 mm2 and consumes 54 mW of power from a 1.8-V supply.
Date of Publication: Jan. 1, 2006