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55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

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5 Author(s)
Kurose, D. ; Corporate R&D Center, Toshiba Corp., Kawasaki, Japan ; Ito, T. ; Ueno, T. ; Yamaji, T.
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A new power reduction technique for ADCs is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique, and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-P 7-M CMOS technology. The 10-bit, 200-MSPS ADCs achieve DNL of 0.66 LSB, rNL of 1.00 LSB, and SNDR of 54.4 dB that corresponds to 8.7 ENOB. The power dissipation is only 55 mW from a 1.2-V supply.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005