Cart (Loading....) | Create Account
Close category search window

A 3.5Gbit/s post-amplifier in 0.18μm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Hermans, C. ; ESAT-MICAS, K.U. Leuven, Belgium ; Steyaert, M.

A postamplifier with output buffer implemented in a standard 0.18μm 1.8V CMOS technology is proposed. Using broadband techniques for both postamplifier and output buffer, highspeed operation has been achieved. For a differential 10mVpp 231-1 pseudo random bit sequence, a bit error rate of 5·10-12 at 3.5Gbit/s has been measured. At lower bitrates the bit error rate is even lower: a 1 Gbit/s 10mVpp, input signal results in a bit error rate of 7·10-14. The rms jitter is 12ps. The postamplifier circuit consumes only 19mA from a 1.8V power supply.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.