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A 3.5Gbit/s post-amplifier in 0.18μm CMOS

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2 Author(s)
Hermans, C. ; ESAT-MICAS, K.U. Leuven, Belgium ; Steyaert, M.

A postamplifier with output buffer implemented in a standard 0.18μm 1.8V CMOS technology is proposed. Using broadband techniques for both postamplifier and output buffer, highspeed operation has been achieved. For a differential 10mVpp 231-1 pseudo random bit sequence, a bit error rate of 5·10-12 at 3.5Gbit/s has been measured. At lower bitrates the bit error rate is even lower: a 1 Gbit/s 10mVpp, input signal results in a bit error rate of 7·10-14. The rms jitter is 12ps. The postamplifier circuit consumes only 19mA from a 1.8V power supply.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005

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