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A 8Kb domino read SRAM with hit logic and parity checker

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4 Author(s)
Pelella, A.R. ; Syst. & Technol. Group, IBM, Poughkeepsie, NY, USA ; Tuminaro, A.D. ; Freese, R.T. ; Chan, Y.H.

An 8Kb domino read SRAM with hit logic and parity checker, fabricated in a 65nm SOI CMOS technology (Leobandung, 2005), is described. A key feature is the elimination of the traditional sense amplifier to reduce timing and design complexity. The focus of this paper is to demonstrate a memory array, comprised of 6T cells, that can generate near "rail-to-rail" bit-line voltage differentials that can be driven off macro without the aid of sense amplifiers. Therefore, short, low capacitance bit-line segments (or sub-arrays) are cascaded together to form larger bit-line structures, achieving performance and density goals with robust operation over a wide range of process and environmental conditions.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005