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/spl mu/Complexity: estimating processor design effort

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3 Author(s)
C. Bazeghi ; Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA ; F. J. Mesa-Martinez ; J. Renau

Microprocessor design complexity is growing rapidly. As a result, current development costs for top of the line processors are staggering, and are doubling every 4 years. As we design ever larger and more complex processors, it is becoming increasingly difficult to estimate how much time it will take to design and verify them. To compound this problem, processor design cost estimation still does not have a quantitative approach. Although designing a processor is very resource consuming, there is little work measuring, understanding, and estimating the effort required. To address this problem, this paper introduces /spl mu/Complexity, a methodology to measure and estimate processor design effort. /spl mu/Complexity consists of three main parts, namely a procedure to account for the contributions of the different components in the design, accurate statistical regression of experimental measures using a nonlinear mixed-effects model, and a productivity adjustment to account for the productivities of different teams. We use /spl mu/Complexity to evaluate a series of design effort estimators on several processor designs. Our analysis shows that the number of lines of HDL code, the sum of the fan-ins of the logic cones in the design, and a linear combination of the two metrics are good design effort estimators. On the other hand, power, area, frequency, number of flip-flops, and number of standard cells are poor estimators of design effort. We also show that productivity adjustments are necessary to produce accurate estimations.

Published in:

38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05)

Date of Conference:

12-16 Nov. 2005