By Topic

Expression synthesis in process networks generated by LAURA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zissulescu, C. ; Leiden Inst. of Adv. Comput. Sci., Netherlands ; Kienhuis, B. ; Deprettere, E.

The COMPAAN/LAURA (Stefanov et al., 2004) tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a process network in which the control is parameterized and distributed. This control is given as parameterized polytopes that are expressed in terms of pseudo-linear expressions. These expressions cannot always be mapped efficiently onto hardware as they contain multiplication and integer division operations. This obstructs the data flow through the processes. Therefore, we present in this paper the expression compiler that efficiently maps pseudo-linear expressions onto a dedicated hardware data-path in such a way that the distributed and parameterized control never obstructs the data flow through processors. This compiler employs techniques like number theory axioms, method of difference, and predicated static single assignment code.

Published in:

Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on

Date of Conference:

23-25 July 2005