Cart (Loading....) | Create Account
Close category search window
 

Single event effects testing of a PLL and LVDS in a RadHard-by-design 0.25-micron ASIC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
4 Author(s)
Hartwell, M. ; Aeroflex Colorado Springs Inc., Colorado Springs, CO, USA ; Hafer, C. ; Milliken, P. ; Farris, T.

SEE testing performed on PLL and LVDS circuits showed both are immune to SEL to a LET of 108 MeV-cm2/mg. Temporary phase shifts and frequency changes caused by SET in the PLL are investigated.

Published in:

Radiation Effects Data Workshop, 2005. IEEE

Date of Conference:

11-15 July 2005

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.