By Topic

Diminished-1 modulo 2n+1 squarer design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
H. T. Vergos ; Comput. Eng. & Informatics Dept., Univ. of Patras, Greece ; C. Efstathiou

Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2n+1. To avoid using (n+1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2n+1 arithmetic applications. In the paper, for the first time in the open literature, the authors formally derive modulo 2n+1 squarers that adopt the diminished-1 number system. The resulting implementations are built using only full-and half-adders and a final diminished-1 adder and can therefore be pipelined straightforwardly.

Published in:

IEE Proceedings - Computers and Digital Techniques  (Volume:152 ,  Issue: 5 )