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Adaptively biased linear transconductor

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1 Author(s)
Sengupta, S. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

This paper describes a new circuit topology of a linear transconductor. The conventional differential pair (CDP), with a constant tail current, is linearized by an adaptive biasing scheme , and the only extra elements added to the differential pair are source followers. Compared to the CDP, the proposed circuit achieves similar speed and noise performance, but the common-mode rejection is compromised at the expense of tremendous improvement in linearity. While operating from a 1.8-V power supply in a 0.18-μm CMOS process, the simulated variation in gm for 1-Vp-p and 2-Vp-p differential input is 1.2% and 22%, respectively. Also, the THD performance for a 1-Vp-p, 1-MHz differential sinusoidal input is -65 dB, which is about a 40-dB improvement over the CDP.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:52 ,  Issue: 11 )