Adaptively biased linear transconductor

This paper describes a new circuit topology of a linear transconductor. The conventional differential pair (CDP), with a constant tail current, is linearized by an adaptive biasing scheme , and the only extra elements added to the differential pair are source followers. Compared to the CDP, the proposed circuit achieves similar speed and noise performance, but the common-mode rejection is compromised at the expense of tremendous improvement in linearity. While operating from a 1.8-V power supply in a 0.18-/spl mu/m CMOS process, the simulated variation in g/sub m/ for 1-V/sub p-p/ and 2-V/sub p-p/ differential input is 1.2% and 22%, respectively. Also, the THD performance for a 1-V/sub p-p/, 1-MHz differential sinusoidal input is -65 dB, which is about a 40-dB improvement over the CDP.