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RF packaging and passives: design, fabrication, measurement, and validation of package embedded inductors

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6 Author(s)
S. A. Chickamenahalli ; Assembly Technol. Dev. & Design Process Dev., Intel Corp., Chandler, AZ, USA ; H. Braunisch ; S. Srinivasan ; Jiangqi He
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Design, modeling, and characterization of inductors embedded in a package substrate promising higher quality factor (Q) and lower cost than on-chip inductors is described. In addition to the problem of large conductor losses, on-die inductors with or without magnetic materials consume considerable die area and require the removal of the first-level interconnect bumps beneath them to maintain a reasonably high Q value. Moving inductors to the package eliminates the need for bump array depopulation and, thus, mitigates the potential reliability problems caused by voids in the epoxy underfill between the die and the substrate. Competency developed to design, fabricate, and characterize inductors based on standard organic flip-chip packaging technology is described. Physical design details along with measurement procedures and results are discussed. In addition, modeling techniques for achieving good correlation to measured data are included.

Published in:

IEEE Transactions on Advanced Packaging  (Volume:28 ,  Issue: 4 )