Cart (Loading....) | Create Account
Close category search window

Cascaded carry-select adder (C2SA): a new structure for low-power CSA design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Yiran Chen ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Hai Li ; Roy, K. ; Cheng-Kok Koh

In this paper we propose a novel low-power carry-select adder (CSA) design called cascaded CSA (C2SA). Based on the prediction of the critical path delay of current operation, C2SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C2SA in 180nm technology show that C2SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) latency per operation (LPO) compared to standard CSA.

Published in:

Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on

Date of Conference:

8-10 Aug. 2005

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.