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Energy-efficient and high-performance instruction fetch using a block-aware ISA

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2 Author(s)
A. Zmily ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; C. Kozyrakis

The front-end in superscalar processors must deliver high application performance in an energy-effective manner. Impediments such as multi-cycle instruction accesses, instruction-cache misses, and mispredictions reduce performance by 48% and increase energy consumption by 21%. This paper presents a block-aware instruction set architecture (BLISS) that defines basic block descriptors in addition to the actual instructions in a program. BLISS allows for a decoupled front-end that reduces the time and energy spent on misspeculated instructions. It also allows for accurate instruction prefetching and energy efficient instruction access. A BLISS-based front-end leads to 14% IPC, 16% total energy, and 83% energy-delay-squared product improvements for wide-issue processors.

Published in:

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

Date of Conference:

8-10 Aug. 2005