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A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

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17 Author(s)
Iida, M. ; Corp. Syst. LSI Dev. Div., Syst. LSI Technol. Dev. Center, Kyoto, Japan ; Kuroda, N. ; Otsuka, H. ; Hirose, M.
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A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 μW are achieved.

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Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 11 )