A monotonic digitally controlled delay element

A monotonic digitally controlled delay element (DCDE) is implemented in the 0.18 /spl mu/m CMOS technology. In this paper, the design procedure of the new architecture and measurement results are reported. The delay of the DCDE changes monotonically with respect to the digital input vector. The monotonicity is one of the important features of this new architecture. Due to its monotonic behavior, the design of the DCDE is rather straightforward. The DCDE can be analyzed by a simple set of empirical equations with reasonable accuracy and can be made more tolerant to process, temperature, and supply voltage variations. The implemented delay element provides a delay resolution of as low as 2 ps and consumes 170 /spl mu/W to 340 /spl mu/W static power depending on the digital input vector.