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A 2.4 GHz CMOS sub-sampling mixer with integrated filtering

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2 Author(s)
H. Pekau ; Dept. of Electr. & Comput. Eng., Univ. of Calgary, Alta., Canada ; J. W. Haslett

A sub-sampling mixer that incorporates sampling switches and hold capacitors into the parallel resonant LC load of an LNA is proposed. The noise figure of the proposed sub-sampling mixer is lower than that of a standard sampling circuit because the proposed mixer has narrow-band gain and input noise filtering properties. A novel level-shifting clock buffer with fast rise and fall times to drive the mixer sampling switches is presented. The mixer was fabricated in a 0.18 μm CMOS process and measured results are presented for an RF input frequency of 2.42 GHz and a sampling frequency of 100 MHz. With a measured noise figure of 21.8 dB, the proposed circuit shows improved performance compared to other published sub-sampling mixers.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:40 ,  Issue: 11 )