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This article is targeted as an introduction to the physics of strained Si and the current state of the art in uniaxial strained Si MOSFET. The first part of the article explains how strain alters the valence and conduction band of Si as well as scattering rates. This is followed by a review of state-of-the-art strained techniques being implemented in 90- and 65-nm process technologies. Finally, we conclude with a discussion of the future scalability of strained Si MOSFETs in the ballistic regime and nanoscale CMOS.