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Real-time Handel-C based implementation of DV decoder

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3 Author(s)
M. Gorgon ; Dept. of Automatics, AGH Univ. of Sci. & Technol., Krakow, Poland ; S. Cichon ; M. Pac

In the paper, an FPGA realization is described for a DV decoder, working in real-time with digital signal conformant to IEC-6 1834-2 standard. The FPGA decoder covers the following stages of the signal decompression: Inverse VLC, Inverse Quantization, Inverse Weighting, Inverse DCT and all the auxiliary operations. Each stage of the operation has been realized by creation of processing element, based on the function codes implemented in Handel-C language. In order to achieve a real-time performance, optimization has been carried out for algorithms and all function codes. Next, a pipeline implementation for the video stream has been completed. Finally, the function execution has been parallelized in the pipeline at the single video block level. Hardware-software test stand has been designed and set-up and then testing has been carried out on real data transmitted on-line from a DV camcorder.

Published in:

International Conference on Field Programmable Logic and Applications, 2005.

Date of Conference:

24-26 Aug. 2005