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Dataflow architectures provide an abundance of computing units that can be statically or dynamically configured to match the computing requirements of the given application. Wire delay has a reduced impact in dataflow architectures because only neighboring architectural entities are allowed to communicate within a single clock cycle. In this paper, we propose MILP-based placement and routing algorithms for mapping dataflow graphs to dataflow machines. The optimization process is guided by profiling information available from the compiler. Our goal is to minimize the total execution time of the given application represented by a dataflow graph under architectural constraints. We propose a hierarchical method to handle the complexity of the initial MILP formulation. Our profile-driven MILP algorithm reduces the total execution time of benchmark applications compared to the conventional wirelength-driven approach on average by 18%.