By Topic

Low temperature wafer-scale 3D ICs: technology and characteristics

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. K. Kim ; Dept. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA ; S. Tiwari

Fabrication techniques that allow wafer-scale transplantation, bonding and interconnecting of fully fabricated device layers with thickness on the order of micrometers are described. The temperature budget of this 3D integration technology is less than 350 °C and the approach utilizes Benzocyclobutene (BCB) as the permanent wafer bonding medium. Alignment registration of several micrometers between donor device layer to the host substrate is achieved. The characterization of devices, structures and process conditions are presented. Also, measurement of heating effects and temperatures in a 3D IC environment is described. The 3D integration approach allows reduction in crosstalk for mixed-signal applications using inter-device layer ground planes. This technique shows -8 dB of crosstalk attenuation between device layers. The newly developed 3D integration fabrication methodology can be extended beyond silicon-based devices to SiGe and III-IV technologies.

Published in:

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

Date of Conference:

9-11 May 2005