Referenced Items are not available for this document.
A concordant memory-array design incorporates device fluctuation statistically into the signal-to-noise ratio analysis in DRAM and represents the failed bits in a chip. The proposed technique gives us a quantitative evaluation of the memory array and assures the operation of the 1.4 V array of a 100 nm - 1 Gb DRAM. The calculated dependence of failed bit counts on the array voltage is in good agreement with the experimental results of a 512 Mbit DRAM chip.
Published in:
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
Date of Conference: 9-11 May 2005
- Page(s):
- 163 - 166
- Print ISBN:
- 0-7803-9081-4
- INSPEC Accession Number:
- 8531370
- Digital Object Identifier :
- 10.1109/ICICDT.2005.1502621
- Product Type:
- Conference Publications
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