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Improvement of non volatile memory tunnel oxide robustness and integrity by design optimization of the memory cell

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7 Author(s)
Ackaert, J. ; AMIS, Oudenaarde, Belgium ; de Backer, E. ; Lowe, A. ; Yao, T.
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During the processing of CMOS with embedded NVM, an issue with the tunnel oxide was discovered. On part of the wafer, the tunnel oxide was very leaky and had a charge to breakdown (QBD) that was close to zero. The sensitivity of a capacitor test structure towards degradation due to the cleaning prior to the oxidation is depending very much on the design of the test structure. A very strong impact of the isolation of the test structure is observed. Gate oxide grown on a P-type well, that is electrically isolated by multiple junctions from exposed N-type well, was found to be very sensitive to Si surface cleaning treatment prior to the oxidation. When both P-type and N-type Si with only a single junction in between are exposed during this cleaning, then the oxide grown in the P-type silicon becomes very robust and insensitive to the surface treatment prior to the oxidation. Evidence is brought that the improvement of this P-type Si is due to the occurrence of an electrolytic cell in the Si during the cleaning. The electrolytic cell is formed by the exposed N- and P-type regions as electrodes and the cleaning chemicals as electrolyte. In this cell, the exposed N-type region is protecting the exposed P-type region against degradation of the Si surface during this cleaning treatment prior to the tunnel oxidation. As far as we know, for the first time it is demonstrated that with the proper design of connected N-type and P-well regions, it is possible to establish a very robust tunnel oxide in a P-type well that is insensitive to process variations during the cleaning of Si prior to the tunnel oxidation.

Published in:

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Date of Conference:

9-11 May 2005