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A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. ∼76M transistors are integrated in a 130nm CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.
Date of Conference: 9-11 May 2005