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A dynamic clock skew compensation circuit technique for low power clock distribution

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3 Author(s)
Yamashita, T. ; Semicond. Technol. Acad. Res. Center, Yokohama, Japan ; Fujimoto, T. ; Ishibashi, K.

Clock tree synthesis (CTS) is an essential technique for SoC design. A dynamic skew compensation technique is proposed here, which relaxes the CTS requirements and contributes to both small skew and low power operation. A test chip has been fabricated using 0.13-μm CMOS technology. Measured results show a 44% skew improvement from a 100-ps initial skew. This technique can be easily implemented in the current CTS flow.

Published in:

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Date of Conference:

9-11 May 2005

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