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Clock tree synthesis (CTS) is an essential technique for SoC design. A dynamic skew compensation technique is proposed here, which relaxes the CTS requirements and contributes to both small skew and low power operation. A test chip has been fabricated using 0.13-μm CMOS technology. Measured results show a 44% skew improvement from a 100-ps initial skew. This technique can be easily implemented in the current CTS flow.