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Clock distribution on the microprocessor codenamed Montecito features four distinct segments and topologies each tuned to a specific purpose. A region based active de-skew (RAD) system reduces the process, voltage, and temperature sources of skew across the 21.5 × 27.7mm2 die during normal operation. Clock vernier devices (CVDs) inserted at each local clock buffer allows 70ps of adjustment via scan. The system supports a constantly varying frequency and consumes less than 25W on its 30mm route from PLL to latch.