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Browse Conference Publications > Consumer Electronics, 2005. ( ... Help

A co-processor architecture for video scan-rate-conversion and spatial/temporal noise reduction

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3 Author(s)
Shaori Guo ; Chien-Hsin Lin ; Zhengyu Zhang

A co-processor architecture for video scan-rate-conversion and noise reduction is presented. Both motion compensated and non-motion compensated deinterlacing and up-conversion algorithms are supported. This enables the co-processor to process both standard definition TV and high definition TV signals at low cost, offering a viable solution for consumer applications.

Published in:
Consumer Electronics, 2005. (ISCE 2005). Proceedings of the Ninth International Symposium on

Date of Conference: 14-16 June 2005

Page(s):
34 - 38
Print ISBN:
0-7803-8920-4
INSPEC Accession Number:
8615733
Digital Object Identifier :
10.1109/ISCE.2005.1502337
Product Type:
Conference Publications

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