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Parallel embedded block coding architecture for JPEG 2000

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5 Author(s)
Hung-Chi Fang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Yu-Wei Chang ; Tu-Chih Wang ; Chung-Jr Lian
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This paper presents a parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000. The architecture is based on the proposed word-level EBC algorithm. By processing all the bit planes in parallel, the state variable memories for the context formation (CF) can be completely eliminated. The length of the FIFO (first-in first-out) between the CF and the arithmetic encoder (AE) is optimized by a reconfigurable FIFO architecture. To reduce the hardware cost of the parallel architecture, we proposed a folded AE architecture. The parallel EBC architecture can losslessly process 54 MSamples/s at 81 MHz, which can support HDTV 720p resolution at 30 frames/s.

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IEEE Transactions on Circuits and Systems for Video Technology  (Volume:15 ,  Issue: 9 )